Universal asynchronous receiver/transmitter (UART) slave device containing an identifier for communication on a one-wire bus
US5862354A · kind A · utility
28Cited by
20References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1996 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Mar 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor system is disclosed wherein said processor system is adapted to communicate over at least one one-wire network utilizing one-wire communications protocol. For the embodiment of the invention in which the processor system acts as a network master, the processor system includes a master UART especially configured to control communications over such network according to one-wire protocol. For the embodiment of the invention in which the processor communicates over two one-wire networks, the processor system includes a first UART which acts as a slave and a second UART which acts as a master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.