Method and apparatus for overriding bus prioritization scheme
US5862355A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 1996 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Sep 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times. The bus arbiter circuit includes circuitry for receiving requests for access to the bus from those of the plurality of devices desiring access to the bus during an arbitration cycle; circuitry for arbitrating access to the bus during the arbitration cycle in response to the received requests, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; circuitry for granting access to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; and circuitry for increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.