Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches
US5862358A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1997 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | May 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided for reducing read latency for an I/O device residing on a first bus having a first, short read latency timeout period. The apparatus includes a I/O bridge on a second bus having a second, longer read latency timeout compared to that of first bus which modifies read transactions into two separate transactions. A first transaction is a write transaction to the same address requested by the read transaction. This transaction forces a write-back if the address hits in a CPU's write-back cache. Thereafter the read transaction is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the first bus having a short read latency timeout period from exceeding it's read latency timeout limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.