Configuration pin emulation circuit for a field programmable gate array
US5862365A · kind A · utility
4Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1996 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Sep 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for providing a pin-for-pin replacement of a field programmable gate array (FPGA). The integrated circuit includes an emulation circuit for mimicking the programmable stage (e.g., initialization, configuration and start-up states) of the FPGA. The integrated circuit is designed to be transparent to the user/customer, thereby eliminating the need for a costly redesign of a user's circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.