Array system architecture of multiple parallel structure processors
US5862397A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1996 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Dec 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system of elementary processors in array form organized in accordance with a plurality of nodes with SIMD operation, each having a plurality of elementary processors connected to one another so as to form a ring of elementary processors, each elementary processor being associated with a connection cell connected to the cells of neighbouring elementary processors in order to form a ring network. Each SIMD node is provided with a memory and addressing module ensuring an addressing independence of the node, as well as a control unit connected to the control units of neighbouring nodes in order to form an internode control network in which priority tokens circulate, each memory and addressing module of a node being connected to the memory and addressing module of neighbouring nodes so as to form an internode data network. The system may find one application in the simulation of fluid flows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.