Fabrication method for chip size semiconductor package
US5863816A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1997 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Sep 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method for a chip size semiconductor package includes the steps of bonding conductive wires on bonding pads formed on an upper surface of a semiconductor chip, putting the semiconductor chip including the bonded conductive wires in an electrolyzer containing an electrolytic solution in such a manner that one end of each of the conductive wires is exposed outside of the electrolytic solution, attaching a plating electrode to an inner wall of the electrolyzer, attaching a conductive plate to serve as a common electrode to the exposed one end of each of the conductive wires; and connecting the conductive plate and the outer wall of the electrolyzer to an electric current source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.