Current mirror current source with current shunting circuit
US5864228A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1997 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Apr 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A stacked current mirror circuit includes four N-channel MOS transistors. One transistor serves as an input device for conducting via its drain, a majority of the reference current. Another transistor is connected as a mirroring device, with its drain coupled to a voltage source, its gate coupled to the gate of the input device, and its source coupled to the source of the input device at a first common node. These two transistors couple to form a first current mirror circuit which couples to the input of a second current mirror comprising the third and fourth transistors. The drain and gate of the third transistor couple to the first common node and the gate of the fourth transistor. The sources of both the third and fourth transistors couple to a second common node (e.g., ground), and the drain of the fourth transistor provides the output. As a result, current is mirrored from the input device transistor to the mirroring device transistor, and then forced through the third transistor. The current is then mirrored from the third transistor to the fourth transistor which forces the current to the output line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.