Method and apparatus for doubling a clock signal using phase interpolation
US5864246A · kind A · utility
20Cited by
13References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for multiplying a clock signal. The circuit includes a phase interpolator having two inputs for receiving complementary clock signals. The output of the phase interpolator is connected to an input in an exclusive OR gate. One of the two complementary input signals also is sent into the exclusive OR gate, wherein a multiplied clock signal is generated at the output of the exclusive OR gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.