Non-servo clock and data recovery circuit and method
US5864250A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1997 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Mar 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery circuit has an input port for receiving a data signal representing a sequence of data values, a pulse generator, a clock generator and a data storage element. The pulse generator generates a pulse whenever a data value change is detected in the received data signal. The clock generator generates a clock signal having an associated frequency and phase. The clock generator receives each pulse produced by the pulse generator so as to synchronize the clock signal's phase with data value changes on the input port. The data storage element stores data values in the data signal at times dictated by the generated clock signal. The data values stored by the data storage element is the recovered data signal and the generated clock signal is the recovered clock signal. The pulse generator and clock signal generator interoperate so as to bound jitter in the recovered clock signal caused by any jitter in the received data signal so that the data values in the received data signal are stored during a data capture time window whose phase position is automatically compensated for the any jitter in the received data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.