Method and apparatus for self-resetting logic circuitry
US5864251A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1997 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Jan 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0966
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.