Circuit arrangement with a filter quadripole
US5864256A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1997 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Mar 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/1615
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A description is given of a circuit arrangement comprising PA1 a filter quadripole having two output terminals and PA1 a voltage follower circuit having two terminals, said terminals having identical electric potentials when the voltage follower circuit is in its turned-on state, each of the terminals of the voltage follower circuit being connected to one of the output terminals of the filter quadripole respectively, and the voltage follower circuit only being in its turned-on state during the turn-on time interval of the circuit arrangement. This circuit arrangement is suitable for a receiver circuit, more particularly, for a pager and has a very brief turn-on time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.