Computer system power management interconnection circuitry, systems and methods
US5864702A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1996 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Nov 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) to the microcomputer integrated circuit (102) and has a second power management circuit logic (1620, 1630) that responds to a plurality of interrupt event inputs (in CSC REGs A, B) and concentrates these inputs to a single card system management interrupt output (CRDSMI#). A peripheral processor integrated circuit (110) has a third power management circuit (920) including a plurality of system management interrupt (SMI) sources, and a SMI unit (2370). The SMI unit (2370) has an output (SMI#) connected to the SMI input of the microprocessor integrated circuit. The SMI unit (2370) responds to the card SMI output of the card interface integrated circuit (112) as well as the plurality of SMI sources. The plurality of SMI sources includes timer circuitry (2350) connected to power down terminals (IDEPWR#, FDDPWR#, SIUPWR#, PCSPWR#) for connection to external peripherals upon respective timeouts…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.