Multimedia processor using variable length instructions with opcode specification of source operand as result of prior instruction
US5864704A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1995 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Oct 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A media engine is disclosed herein which incorporates into a single chip structure the seven multimedia functions of video, 2D graphics, 3D graphics, audio, FAX/modem, telephony, and video-conferencing. In accordance with the present invention, a media engine includes a signal processor which shares a memory with the CPU of the host computer and also includes a plurality of control modules each dedicated to one of the seven multi-media functions. The signal processor retrieves from this shared memory instructions placed therein by the host CPU and in response thereto causes the execution of such instructions via one of the on-chip control modules. The signal processor utilizes an instruction register having a movable partition which allows larger than typical instructions to be paired with smaller than typical instructions. The signal processor reduces demand for memory read ports by placing data into the instruction register where it may be directly routed to the arithmetic logic units for execution and, where the destination of a first instruction matches the source of a second instruction, by defaulting the source specifier of the second instruction to the result register of the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.