Communication system which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency
US5864714A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1996 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Apr 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus for and method of implementing a novel buffer ba full duplex communication system is disclosed. The disclosed invention is particularly useful in native sign processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, echo canceler. CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communication system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel buffer switching mechanism to optimize the tradeoff between processing response time, on one hand, and robustness to interrupt latency and processor implementation on the other hand. The internal processing of the modem works on a buffer full of samples once every time slice thus reducing the probability of a buffer underrun/overrun error occurring. The reduction in probability of data underrun/overrun is achieved by increasing the buffer size, thus giving the operating system greater leeway in choosing th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.