Modified zero layer align method of twin well MOS fabrication
US5866447A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1996 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Oct 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating alignment marks in a twin-well integrated circuit without using a zero-layer photomask is disclosed. This method involves the steps of: (a) forming a pad oxide layer on a P-type semiconductor wafer; (b) obtaining an N-well photomask containing an N-well pattern for defining an N-well region in the P-type semiconductor wafer and an alignment mark pattern for defining a plurality of alignment marks in the P-type semiconductor wafer, the N-well photomask is designed such that the alignment mark pattern and the N-well pattern can be separately exposed; (c) using a photolithography technique to expose only the alignment mark pattern to form a plurality of the alignment marks in the pad oxide layer and the P-type semiconductor wafer; (d) coating a first photoresist layer overlaying the pad oxide layer which is aligned using the alignment marks formed in step (b); (e) using the N-well photomask to pattern the first photoresist layer and define the N-well region; and (f) ion-implanting N-type impurities to form the N-well region in the P-type semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.