Method for fabricating a semiconductor memory device
US5866456A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 1996 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Sep 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/65
Abstract
A semiconductor memory device is provided which includes: a memory cell portion including at least one gate electrode formed on a semiconductor substrate and a plurality of source/drain regions formed in the semiconductor substrate and extending parallel to each other and perpendicular to the gate electrode, the gate electrode and the plurality of source/drain regions constituting a plurality of first conductivity type channel transistors; and a peripheral circuitry portion including a first conductivity type channel transistor having a gate electrode formed on the semiconductor substrate and source/drain regions; wherein channels of the first conductivity type channel transistors in the memory cell portion each have a higher impurity concentration than a channel of the first conductivity type channel transistor in the peripheral circuitry portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.