Multiplexed output circuit and method of operation thereof
US5867053A · kind A · utility
6Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1997 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Mar 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplexed output circuit (200) for use in an integrated circuit (500) such as a static random access memory locates a plurality of amplifiers (206, 208), a plurality of output buffers (210, 212), and an output driver (201) on the integrated circuit (500), such that the routing parasitic delay between the plurality of output buffers and the output driver (218-224) is greater than the routing parasitic delay between any output buffer (e.g. 212) and its corresponding amplifier (e.g. 206).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.