Programmable memory device that supports multiple operational modes
US5867444A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1997 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Sep 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory device including a register that stores a programmable mode select bit, a data input, a control input and decode circuitry that decodes the mode select bit to determine whether the memory device operates in either a check mode or a mask mode. The control input receives at least one control bit for each data byte received by the memory device during a write operation or cycle. The function of the control bit(s) depends upon the mode select bit. In a check mode of operation, each control bit functions as a parity/check bit for a corresponding data byte, where the memory device stores the check bit with its corresponding data byte during each write cycle. In the mask mode of operation, each control bit functions as a mask bit for a corresponding data byte, where the memory device selectively stores or masks the data byte depending upon the state of the corresponding mask bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.