Buffer for memory modules with trace delay compensation
US5867448A · kind A · utility
29Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1997 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Jun 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprising a generation circuit for providing a clock signal. A number of compensation circuits may receive the clock signal and may present essentially simultaneously a compensated clock signal at their outputs. The compensated clock signals are generally presented to a plurality of synchronous external devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.