System and method to coherently and dynamically remap an at-risk memory area by simultaneously writing two memory areas
US5867642A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1995 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Aug 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system comprising a CPU, main memory, and a memory controller, a system and method to dynamically remap memory while maintaining memory coherency. The main memory is divided into memory areas, one of which is a reserve memory area. Memory accesses are checked for errors and the errors are logged, as is the memory area in which the error occurred. The error log for each memory area is compared to an acceptable error frequency level. If a particular memory area exceeds the acceptable error frequency level, the memory area will be dynamically remapped to the reserve memory area while memory coherency is maintained. The dynamic remapping is performed by copying the memory from the memory area which exceeded the acceptable error frequency level, to the reserve memory are. During the copying, all writes to the memory area which exceeded the acceptable error frequency level are concurrently performed to both the memory area which exceeded the acceptable error frequency level and to the reserve memory area, thus preserving memory coherency. Also, the copying is performed in small blocks to avoid system timing problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.