Microprocessor system for handling multiple priority levels interrupt requests to processor and interrupt process identifiers
US5867687A · kind A · utility
12Cited by
12References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 3, 1996 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | May 3, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed control circuitry for, and a method of controlling, multiple priority level interrupt request to a microprocessor in which output circuitry for outputting an interrupt identifier is operable only in response to an interrupt signal having a higher priority status than any currently executing interrupt process, and a microprocessor system and method of controlling a microprocessor system, incorporating such circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.