System for data transfer across asynchronous interface
US5867731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1996 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Aug 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/46
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for use in transferring data packets across different clock domains using an input data register for receiving a block of data packets with the input data register and a plurality of interface registers located in the first clock domain for transferring a block of data packets from the input register to a second clock domain in response to a request signal with the system prioritizing the transfer of multiple data packets within the block of data packets by length in order to transfer the longer word packets first and the shorter word packets last with the shortest word packets within the block bundled together and simultaneously transferring across an asynchronous interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.