Ultra thin tunneling oxide using buffer CVD to improve edge thinning
US5869370A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Dec 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of forming a tunneling oxide film having a uniform thickness in the fabrication of a Flash EEPROM memory cell is described. A first oxide layer is provided on the surface of a semiconductor substrate wherein a portion of the first oxide layer is removed to expose the semiconductor substrate wherein the exposed portion of the semiconductor substrate comprises a tunneling window. A second oxide layer is deposited within the tunneling window. Thereafter, a thermal oxide layer is grown underlying the first oxide layer and the second oxide layer within the tunneling area wherein the presence of the second oxide layer provides for a uniform thermal oxide thickness throughout the tunneling window and wherein the second oxide layer and the thermal oxide layer together within the tunneling window form the tunneling oxide film in the fabrication of a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.