Transistor fabrication method
US5869375A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Feb 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0275
Abstract
A method for fabricating a transistor includes the steps of forming a gate insulation film on a substrate, forming a gate electrode on the gate insulation film and forming a first insulation film pattern on the gate electrode. A side wall spacer is formed at side surfaces of the first insulation film pattern and the gate electrode. The gate insulation film is etched to expose a portion of a surface of the substrate. An epitaxial layer is formed on the substrate where the gate insulation film is etched. The side wall spacer is removed and a thermal oxide film is grown on a portion corresponding to where the side wall spacer is removed and on an upper portion of the epitaxial layer. A source/drain region is formed by ion-implanting an impurity into the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.