Power level sense circuit
US5869986A · kind A · utility
7Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Jun 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power level sense circuit which is substantially immune to variations in integrated circuit processing and operating temperature. The sense circuit uses a diode biased to a predetermined average conduction level as the primary element in an envelope detector to detect the envelope of the RF transmit signal. While the DC offset of the diode will vary with temperature and integrated circuit processing, the DC offset is eliminated by an auto zeroing procedure before each power sensing cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.