Information encoding by multiple line selection
US5870326A · kind A · utility
11Cited by
5References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Aug 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved storage circuit that allows multiple bits to be encoded and stored using a single storage element. The encoded information is defined by a coupling made between a transistor as the storage element and any one of several bit lines associated with the transistor. When the coupled bit line is discharged in response to a wordline signal, the stored information can be captured by an encoder. The circuit is particularly useful for efficiently storing information in a gate array integrated circuit, because the gate array has more space around each transistor to add bit lines than a conventional, densely packed, ROM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.