Satellite receiver tuner chip having reduced digital noise interference
US5870439A · kind A · utility
53Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Jun 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3863
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip having digital interface signals. The tuner chip is configured to receive the digital signals at a reduced peak-to-peak amplitude to reduce the digital interference noise in the tuner chip. The digital signals may also have a limited slew rate to further reduce the digital interference noise. The tuner chip is configured to convert a receive signal to a baseband signal, and the demodulator/decoder chip is configured to convert the baseband signal to a decoded signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.