Method and apparatus for providing an optimized compare-and-branch instruction
US5870598A · kind A · utility
72Cited by
7References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimized compare-and-branch instruction for execution in a RISC type microprocessor. An instruction sequencer implemented in the microprocessor is responsive to a compare-and-branch instruction for efficient execution. The instruction sequencer detects a compare-and-branch instruction and executes it as a regular compare instruction. On the next cycle the instruction sequencer translates the instruction into a branch instruction and provides the translated instruction for execution by one of the execution units. The branch is executed, either taken or not taken, and normal program flow continues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.