Level detector circuit, interface and method for interpreting and processing multi-level signals
US5872468A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/082
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
To decode an attenuated multi-level signal (42) in a receive interface (120) of communication apparatus, first (134) and second (150) diode pumps co-operate with a biasing chain to ensure that threshold reference levels used by respective positive (52) and negative (54) data comparators are dynamically adjusted to a level dependent upon the attenuated multi-level signal (42) applied to the diode pumps. Particularly, a voltage divider (138-144) acts dynamically to bias differential inputs to the respective positive (52) and negative (54) data comparators, with a ratio between a biasing chain of resistors (138-144) and a common input resistor 128 determining the threshold reference levels used to assign logical levels for the reconstruction of symbols encoded within the multi-level signal (42).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.