Pipelined sample and hold circuit with correlated double sampling
US5872470A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1996 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Nov 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a time multiplexed integrating amplifier circuit in which the output circuit is a pipelined sample and hold circuit which provides time multiplexed input signal samples and the feedback integration capacitor is discharged between samples. At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.