Multi-state Josephson memory
US5872731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1997 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Oct 10, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S505/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I.sub.c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I.sub.g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I.sub.con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8. In a preferred embodiment, a plurality of SQUID memory cells 70a, 70b, . . . 70f are arranged in a plurality of columns and rows with column select inputs 72, 74 and row select inputs 76, 78 and 80. Digital-to-analog converters 86 and 88 are preferably provided to convert a binary digital input int…
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