Method and apparatus for scan testing of multi-phase logic
US5872795A · kind A · utility
4Cited by
1References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for using a test signal being computed by applying a combinational test pattern generation tool to a model of the apparatus in which at least one of an at least one sequential device is modelled as a non-sequential device, the apparatus having a first scan cell configured to receive the test signal and drive a first signal in response to a first clock phase; a sequential logic block having the at least one sequential device, the sequential logic block being configured to generate a second signal, at least one of the at least one sequential device being a non-scan cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.