Computer system using a master processor to automatically reconfigure faulty switch node that is detected and reported by diagnostic processor without causing communications interruption
US5872904A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1996 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | May 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13332
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .left brkt-top. log.sub.b N .right brkt-top. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .left brkt-top. log.sub.b N .right brkt-top. indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.