Method and apparatus for parallel high speed data transfer
US5872959A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1996 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Sep 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention concerns a method for eliminating or reducing clock skew introduced by differing signal propagation delays across a data bus. At high bus clock frequencies the time delay differences caused by path length differences can be catastrophic and must be eliminated by expensive layout techniques. An input/output (I/O) architecture is proposed here which tailors a delay to each individual data line, and thereby aligns all the incoming data. Furthermore, a clock signal is provided to indicate the optimal data sampling time. In the described embodiment, this circuit enables the transmission of four 32 bit words in parallel in one clock cycle of a 250 MHz processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.