Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructions
US5872960A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1996 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of com…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.