Reducing the elapsed time period between an interrupt acknowledge and an interrupt vector
US5872982A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1996 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Jul 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, in one aspect, the invention features a method for reducing the elapsed period between the time an interrupt acknowledge is issued by a CPU and the time when the corresponding interrupt vector is received at the CPU. When a device connected to a lower speed bus sends an interrupt request, an interrupt queue device, connected to the CPU by a higher speed bus, intercepts the interrupt request, temporarily stores the corresponding interrupt vector and then responds to an interrupt acknowledge from the CPU by delivering the temporarily stored interrupt vector on the higher speed bus. In addition, the interrupt queue can deliver the temporarily stored interrupt vector to the CPU on a separate serial line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.