System and method for avoiding bus contention on a multiplexed bus by providing a time period subsequent to a read operation
US5872992A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1995 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Aug 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface unit within a processor ensures a delay period after the occurrence of a read operation to avoid bus contention on a multiplexed bus, When there is a requirement for a back-to-back read or write operation subsequent to the read bus cycle on a multiplexed bus it is important to allow devices, such as memory, sufficient time to reset after transmission of data. To avoid the bus contention problem that occurs after a read bus cycle, i.e, prevent a next address on the bus until the bus is in a tri-state condition, one embodiment inserts idle clock cycles subsequent to a read but not subsequent to a write, The present invention avoids bus contention on a multiplexed bus while providing flexibility in interfacing with a variety of memory devices, and providing a flexible processor design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.