Carry-select adder with pre-counting of leading zero digits
US5875123A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 1997 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | May 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.