Method and system for halting processor execution in response to an enumerated occurrence of a selected combination of internal states
US5875294A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1995 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Jun 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system within a data processing system are disclosed for halting execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal states within the processor. The processor includes a number of state machines and a means for monitoring the states of the number of state machines. According to the present invention, a selected combination of states of a subset of the state machines is specified. An enumerated occurrence of the selected combination of states of the subset of the state machines is then detected. In response to the enumerated occurrence of the selected combination of states, execution of instructions by the processor is halted such that states of the number of state machines within the processor remain substantially unchanged following the enumerated occurrence of the selected combination of states. In a first embodiment of the present invention, the selected combination of states is specified as a combination of states corresponding to an access to a specified address within an associated memory. According to a second embodiment of the present invention, the selected combination of states is specified a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.