Instruction format for ensuring safe execution of display list
US5875295A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer controlled graphics system, processes are provided for detecting errors incurred in a display list having variable length instruction/parameter (I/P) sets, the errors occurring during parameterization, transmission, branching, and storage of the display list. Each process includes generating a display list including I/P sets, each I/P set including n parameter words following an instruction word. In each embodiment, a display list is encoded, transmitted, stored in a memory unit, and verified. In one embodiment, the display list is encoded by storing into each instruction word of each I/P set a parity bit of a value representative of the parity of the whole I/P set. In another embodiment, the display list is encoded by storing within each instruction word of each I/P set an m-bit checksum value. The m-bit checksum value is generated by partitioning each I/P set into y m-bit partitions which are summed, ignoring overflow. In a third embodiment, a display list is encoded by appending each I/P set with a checksum word generated by summing the instruction word and each of the n parameter words of each I/P set, ignoring overflows. In each embodiment, the encoded display li…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.