Method and apparatus for multiple channel direct memory access control
US5875352A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1995 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Nov 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports multiple virtual channels in a high speed network interface. When an access to a particular channel state is performed, e.g., by a host processor or the DMA device, the cache is first accessed and if the state information is not located currently in the cache, external memory is read and the state information is written to the cache. As the cache does not store all the states stored in external memory, replacement algorithms are utilize to determine which channel state information to remove from the cache in order to provide room to store a recently accessed channel. A doubly linked list is used to track the most recently used channel. As cached channel information is accessed, the corresponding entry is moved to the top of the list. The doubly linked list provides a rapid apparatus and method for updating pointers to the cache. Top and bottom pointers are maintained, pointing to the most recently used and least recently used channels. When a channel is used, it moved to the top of the list. When channel data is moved from…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.