Cache control circuit having a pseudo random address generator
US5875465A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1997 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Apr 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.