Self-aligned power field effect transistor in silicon carbide
US5877041A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
Abstract
The present invention is directed to a silicon carbide field effect transistor. The FET is formed on a silicon carbide monocrystalline substrate. An insulative material gate having a pair of spaced apart sidewalls is patterned on the substrate. The insulative material comprises a first insulation material overlayed by an electrically conductive layer. Within the substrate is lightly doped base regions located partially under the sidewalls of the gate and extending into the exposed substrate. Associated with the lightly doped base regions are heavily doped source regions aligned with the exposed substrate. On the underside of the substrate is a drain region to form the FET. Further in accordance with the present invention, a method to fabricate a field effect transistor is disclosed. The transistor is formed in a monocrystalline substrate of silicon carbide. Forming a transistor on the silicon carbide substrate entails depositing a first electrically insulative layer over the substrate. Next, an electrically conductive layer is deposited over the first insulative layer and then a second electrically insulative layer is deposited over the conductive layer. The following step includes…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.