System and method for implementing an overlay pathway
US5877741A · kind A · utility
132Cited by
28References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1996 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Apr 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method for processing overlay display data. A display FIFO pipeline processes background graphics display data and a separate overlay FIFO pipeline processes overlay display data stored in an off-screen part of a graphics memory. The overlay FIFO pipeline performs format conversion, interpolation and scaling on the overlay display data and outputs it to an overlay mux. The overlay mux selects between the outputs of the display FIFO pipeline and the overlay FIFO pipeline in the processing of each scan line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.