Folded analog signal multiplier circuit
US5877974A · kind A · utility
5Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 11, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Aug 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four-quadrant analog signal multiplier circuit with a folded cascode differential input stage allows such circuit to be operated at lower power supply voltage potentials, while allowing the same transistor types to be used for both sets of input signals thereby providing for more closely matched input device characteristics and signal gains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.