Data-bit redundancy in semiconductor memories
US5877992A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Dec 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides a data bit redundancy method and apparatus that permits the replacement of faulty bitlines on a data bit basis as opposed to a column address basis. This invention provides a semiconductor memory device having memory cells arranged in columns and rows. Normal local data lines are connected to a global data line via a first switch. A redundant memory data line is connected to the global data line via a second switch. A control generating first and second control signals are coupled to the respective first and second switches for operating the switch in response to a status of a fuse component, whereby when the fuse is intact the normal data lines are connected to the global data line and when the fuse is blown the redundant data lines are connected to the global data line, thus not requiring additional redundancy address decoding circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.