Method and apparatus for verifying a single phase clocking system including testing for latch early mode
US5878055A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Dec 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus are provided for efficiently verifying an on-chip single phase clocking system including testing for latch early mode. A variable delay clock circuit is provided for generating a plurality of delayed clock signals. A delay control register is selectively coupled to the variable delay clock circuit for controlling a delay value of each of the plurality of delayed clock signals. A scan control logic is coupled to the variable delay clock circuit for controlling an operational mode of the variable delay clock circuit. A plurality of latches having a clock input and a data input are coupled to the variable delay clock circuit. Each latch receives a respective one of the generated plurality of delayed clock signals and a data input signal is applied to the data input of a first one of the plurality of latches. The plurality of latches are connected in a chain with a respective latch output connected to a data input of a next latch and a last latch output of the plurality of latches provides an output data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.