Providing serial data clock signal transitions with parity bits
US5878061A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Oct 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4906
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A word of data bits is received and a plurality of parity bits for serial transmission of the data bits is generated. The word of data bits and plurality of parity bits are transmitted, wherein the parity bits are generated and transmitted with the data bits, wherein the parity bits are generated in accordance with a parity scheme that ensures that at least one binary transition occurs within each set of n consecutively transmitted bits, wherein n is a specified number. In another embodiment, a serially-transmitted code word comprising a word of data bits and a plurality of parity bits is received, wherein the parity bits are generated by an encoder and transmitted with the data bits, wherein the parity bits are generated in accordance with a parity scheme that ensures that at least one binary transition occurs within each set of n consecutively transmitted bits, wherein n is a specified number. A parity bit syndrome is generated from the code word, and data correction or detection is performed on the code word in accordance with the parity bit syndrome.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.