Signal processing delay circuit
US5878097A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1997 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | May 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.