Compressed instruction format for use in a VLIW processor and processor for processing such instructions
US5878267A · kind A · utility
42Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 1998 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.